The present invention relates to a production method of a semiconductor device, and specifically to a production method of a semiconductor device having a high stress migration (SM) resistance.
Conventionally, aluminum has been mainly employed as a wring material for an LSI circuit formed on a semiconductor substrate of silicon. In recent years, on the other hand, copper has been receiving more attention as the wiring material along with an increase in the integration degree and an increase in the processing speed of semiconductor integrated circuits, because copper has a lower resistance and higher electromigration (EM) resistance as compared with aluminum. Moreover, as a method for forming a copper film, the electrolytic plating method has been employed because this method can readily and sufficiently fill a trench or hole with the copper film.
FIGS. 6A to 6D are cross-sectional views which illustrate a conventional production method of a semiconductor device. Specifically, these figures illustrate respective steps of a conventional method for forming copper wires.
In the first place, as shown in FIG. 6A, a first insulating film 2 including first copper wires 3 buried therein is formed on a semiconductor substrate 1 having a semiconductor element (not shown) formed thereon. Then, a second insulating film 4 is formed on the first insulating film 2. Thereafter, in the second insulating film 4, holes 5 are formed so as to reach the first copper wires 3, and wire trenches 6 are formed so as to communicate with the holes 5.
Next, as shown in FIG. 6B, a barrier film 7 of tantalum (Ta) having a thickness of about 30 nm and a seed layer 8 of copper (Cu) having a thickness of about 150 nm are sequentially formed by sputtering over the entire surface of the second insulating film 4 which includes the bottom and walls of the holes 5 and the wire trenches 6.
Next, as shown in FIG. 6C, a copper film 9 is deposited by an electrolytic plating method so as to completely fill the holes 5 and the wire trenches 6. Thereafter, for the purpose of stabilizing the copper film 9, the copper film 9 is annealed at 200° C. for about 60 minutes. As a result, the seed layer 8 and the copper film 9 are integrated (hereinafter, a resultant film formed by integrating the seed layer 8 and the copper film 9 is simply referred to as “copper film 9”).
Next, parts of the copper film 9 and barrier film 7 which extend out of the wire trenches 6 are removed using a chemical-mechanical polishing (CMP) method. As a result, second copper wires 9A are formed on the barrier film 7 in the holes 5 and the wire trenches 6 as shown in FIG. 6D.
In the conventional copper wire formation method illustrated in FIGS. 6A to 6D, some problems occur due to stress migration (SM).
The present inventors studied the problems and found the causes thereof. Specifically, we found that at the steps subsequent to the formation of copper wires, for example, at the step of depositing a silicon nitride film or interlayer dielectric on the copper wires or at the step of a sintering process, a wafer is heated so that the copper film is re-crystallized, and accordingly, voids are formed in the copper film. For example, in the case where after the formation of the second copper wires 9A at the step of FIG. 6D, a silicon nitride film 10 and a third insulating film (interlayer dielectric) 11 are sequentially formed on the second copper wires 9A, voids 12 are formed in the second copper wires 9A because of the above-described mechanism. As a result, the production yield of the semiconductor device decreases. Moreover, even after a semiconductor device is shipped as a final product, voids are formed in the copper wires due to heat generated during the operation of the semiconductor device, and as a result, the reliability of the semiconductor device decreases. One possible method for preventing the formation of voids at the steps subsequent to the copper plating and during the operation of the semiconductor device is to sufficiently anneal the copper film immediately after the copper film is plated. However, in the case where the copper film 9 is annealed at 300° C. for about 60 minutes after the holes 5 and the wire trenches 6 are filled with the copper film 9 using an electrolytic plating method at the step of FIG. 6C, a problem shown in FIG. 8 occurs. That is, voids 13 are formed in the portions of the copper film 9 which are provided inside the holes 5 and the wire trenches 6 because the annealing temperature is too high.
As described above, the conventional method involves a trade-off relationship. That is, if the temperature of annealing performed immediately after the copper plating is high, voids are formed at this annealing step. On the other hand, if the annealing temperature is low, voids are formed at a subsequent step or during the operation of the semiconductor device.